There have been known an A/D conversion unit having an offset canceling function for eliminating or canceling out the offset error involved in the A/D converter of the unit (see, for example, Japanese Patent Application Laid Open No. 2003-264462).
FIG. 6 shows a circuit arrangement of an A/D conversion unit having a conventional offset canceling function as disclosed in FIG. 7 of the patent application cited above.
As shown in FIG. 6, the A/D conversion unit has an A/D converter 60 for converting an analog input voltage Vin into a digital output voltage Vout, wherein, and hereinafter as well, digital voltage means voltage of a digitized signal.
The A/D converter 60 has an offset error, which causes the A/D converter to output a non-zero voltage if the input thereto were zero voltage. In order to remove the offset error, the converter 60 is provided with an analog offset canceller 70, a digital-to-analog (D/A) converter 80, an offset operation unit 90, and an input changeover switch SW1.
In the example shown in FIG. 6, the changeover switch SW1 is thrown to a contact point 2 to obtain the voltage to be input to remove the offset error (the voltage referred to as the offset canceling voltage), which causes the ground potential Vgnd (or zero voltage) to be supplied to the positive (+) input terminal of the analog offset canceller 70 serving as a subtracter. The voltage of the negative (−) input terminal of the analog offset canceller 70 is also zero at this stage. The output voltage of the analog offset canceller 70 is supplied as the analog voltage Va to the A/D converter 60, which converts the input voltage into a digital voltage Vd prior to providing it as the output voltage Vout from the conversion unit.
The output voltage Vout would be zero if the A/D converter 60 and the analog offset canceller 70 had no offset error. In actuality, however, the A/D converter 60 and the analog offset canceller 70 have offset errors so that the output voltage Vout of the A/C conversion unit is offset by a certain offset voltage Vofs.
The offset operation unit 90 has an integration circuit adapted to process the offset voltage Vofs to obtain a digitized offset canceling voltage Aofsd for canceling out the offset voltage Vofs. This digitized offset canceling voltage Aofsd is converted into an analog offset canceling voltage Aofs by the D/A converter 80. The analog offset canceling voltage Aofs is input into the negative (−) input terminal of the analog offset canceller 70.
The changeover switch SW1 may be thrown to a contact point 1 with the analog offset canceling voltage Aofs applied to the negative (−) input terminal of the analog offset can celler 70, so that the analog input voltage Vin is input into the positive (+) input terminal of the analog offset canceller 70.
Under this condition, the offset errors of the A/D converter 60 and the analog offset canceller 70 will cancel out, causing the A/D conversion unit to provide an output voltage Vout in accord with the input voltage Vin.
However, the A/D converter 60 of the A/D conversion unit disclosed in the cited patent application has a linearity error Vofs-ad. In addition, the D/A converter 80 provided to remove the offset error presents a further linearity error Vofs-da and a matching error Vofs-m associated with matching between the D/A converter 80 and the A/D converter 60. Moreover, fluctuations Vofs-wn due to white noise also add to the errors.
It is noted that, although the offset voltage that remain in the A/D conversion unit (referred to as residual offset voltage) can be reduced by raising the accuracy of offset canceling capabilities of the A/D and D/A converters 60 and 80, respectively, the residual offset voltage of the converters will not be totally cancelled out. Further reduction of the residual offset voltage can be anticipated by increasing the number of sampled data for offset cancellation, which, however, will require an adversely long time to obtain the offset canceling voltage. Anyway, it is not possible with the prior art A/D conversion unit cited above to completely eliminate the offset voltage from the A/D conversion unit.
It should be noted that the prior art circuit for canceling the offset inevitably has a large size due to the fact that the D/A converter 80 requires the same bit number (16 bits for example) as the A/D converter 60.
When the analog input voltage Vin has a predetermined non-zero voltage level (hereinafter referred to as central voltage) Vctr superimposed on an input signal voltage Vsig, exhibiting a waveform similar to that of an RF modulation signal, it is also necessary to eliminate the offset voltage contained in the central voltage Vctr. However, in obtaining the offset canceling voltage, the analog input voltage Vin is set to zero in the conventional A/D conversion unit, so that the offset voltage or the central voltage Vctr cannot be eliminated. As a consequence, if the analog voltage Va saturates in the A/D conversion unit, the input voltage will be truncated (that is, its waveform will be clipped), thereby presenting an additional problem that the input signal voltage Vsig cannot be accurately converted into a correct digital signal.